Ongoing efforts are being made to enhance carrier mobility in semiconductor devices to increase performance and/or reduce power consumption. The forming of stressed silicon channels by deforming the source/drain region is a known practice. Stress, sometimes referred to as strain, can enhance electron and hole mobility. The performance of a metal-oxide-semiconductor (MOS) device can be enhanced through a stressed-surface channel.
Typically, it is preferred for NMOS devices to have tensile stresses in their channel regions. It is also possible for NMOS devices to benefit from compressive stress in out of plane direction perpendicular to the channel region. PMOS devices benefit from either having compressive stresses in their channel regions and/or from tensile stress in out of plane direction perpendicular to the channel region. Stresses in channel regions can be applied by forming stressed source/drain regions, stressed gate electrodes, stressed contact etch stop layers, etc. One of the methods for applying a beneficial stress to a gate electrode of an NMOS device is to form a stress memorization layer, wherein a typical formation process includes blanket forming a stress memorization layer having an inherent stress, performing an annealing, and then removing the stress memorization layer. The beneficial stress, which is a tensile stress in the channel region and/or a compressive stress in an out-of-plane direction perpendicular to the channel region, is thus “memorized” by the source/drain regions and is imparted onto the channel region of the NMOS device or PMOS device.